1. Field of the Invention
The present invention relates to liquid crystal display domain. More particularly, the present invention relates to a liquid crystal display device that is capable of reducing parasitic capacitance of gate lines.
2. Description of the Prior Art
FIG. 1 is a schematic diagram of the structure of a liquid crystal display device of conventional techniques where the liquid crystal display device 100 comprises a first substrate 110, a second substrate 120 and a liquid crystal layer 130 disposed between the first substrate 110 and the second substrate 120. The first substrate 110 comprises gate lines and a first transparent electrode, and the second substrate 120 is provided with a second transparent electrode 121.
In conventional liquid crystal display devices, a parasitic capacitance in the gate line 111 is the main reason to causes its signal delay. Supposing that the parasitic capacitance is oversized, serious signal delay would give rise to color spots (mura) on the liquid crystal display device 100.
The parasitic capacitances existed in the gate line 111 comprise the following two categories:    1.) The parasitic capacitance forms between the gate line 111 and the data line (not shown in the figure) (the insulation thin film layer between the gate line 111 and the data line is acted as the dielectric medium);    2.) The parasitic capacitance forms between the gate line 111 and the second transparent electrode 121 on the second substrate 120 (the liquid crystal layer 130 is acted as the dielectric medium).
Accordingly, to reduce the two categories of parasitic capacitances in the gate line is the goal for the designers of the liquid crystal display device to endeavor.
Therefore, it is quite imperative to provide a liquid crystal display device, to settle the existing issues of the conventional techniques.